Recrutement de 01 ASIC Top-Level Physical Design Engineer, Google Cloud
Recrutement de 01 ASIC Top-Level Physical Design Engineer, Google Cloud
Entreprise: Google
Niveau d'etude: BAC + 4
Localité: Etats-Unies / Washington
Date limite: 2023-02-16
ASIC Top-Level Physical Design Engineer, Google Cloud
Google
In-office:
Sunnyvale, CA, USA
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Qualifications
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
7 years of experience with physical design including pin, signal, floor planning, IP integration, analog routing, and global clocking.
Experience in hierarchical PnR construction in modern process nodes,full-chip timing closure, design rules and considerations, critical dimensions, multi-patterning, latch-up, etc.
Preferred qualifications:
Experience in chiplet/interposer 2.5D IC co-design.
Experience in low power design implementation, multi-voltage domains, and power gating.
Experience in scripting languages such as Python, TCL, or Perl.
Knowledge of design for manufacturability and yield.
Familiarity with thermal and electrical power considerations, and analysis.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Additional Information:
The US base salary range for this full-time position is $166,000-$262,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
Perform top-level physical design including pin, signal, floor planning, IP integration, analog routing, global clocking.
Utilize an understanding of hierarchical PnR (Place and Route) construction in modern process nodes, timing budgeting, full-chip timing closure, design rules and considerations (e.g., critical dimensions/spacing, multi-patterning, latch-up rules, etc.) to contribute to or lead full-chip physical implementation.
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